부산대학교 도서관

In digital circuits, aging phenomena can lead to timing violations due to increased signal delays suffered by digital cells. An accurate and trustworthy characterization of these mechanisms in modern nanometer CMOS technologies is essential, for which accelerated aging tests are the typical experimental procedure used. This type of test makes it possible to observe aging degradation without waiting for years of circuit operation, by raising voltage and temperature conditions above their nominal values. These stress conditions have a major impact on how the cell under test will be affected by aging degradation. This paper presents a new highly versatile test module whose purpose is to generate AC and DC signals with different amplitudes and, in the case of AC signals, also with different frequencies, to stress a digital cell in a wide variety of scenarios.