부산대학교 도서관

In this study, we present a low-phase-noise 20-GHz phase-locked loop (PLL) with simultaneous $g_{m}$ -boosted and third-harmonic impedance-tuned voltage-controlled oscillator (VCO). The proposed PLL is implemented using the 65-nm CMOS technology. By both implementing a cross-coupled center-tapped inductor and controlling the harmonic impedance, the phase noise is improved by approximately 3.4 dB. An auxiliary cross-coupled pair (CCP) is used to boost the transconductance, while a parallel quarter-wave open stub is added to minimize the second-harmonic impedance for the output signal as the squared waveform. The proposed PLL demonstrated a measured phase noise of −102.05 dBc/Hz at a 1-MHz offset frequency. Based on the measured phase noise, the proposed PLL can achieve a figure of merit (FOM) of −174.35 dBc/Hz, while it consumes 23.6 mW with a supply voltage of 1 V.