학술논문
Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance
Document Type
Conference
Author
Kobrinsky, M.; Silva, J. D; Mannebach, E.; Mills, S.; Qader, M. Abd El; Adebayo, O.; Radhakrishna, N. Arkali; Beasley, M.; Chawla, J.; Chugh, S.; Dasgupta, A.; Desai, U.; Re, E. De; Dewey, G.; Edwards, T.; Engel, C.; Gudmundsson, V.; Hicks, J.; Krist, B.; Mehandru, R.; Meric, I.; Morrow, P.; Nandi, D.; Patel, P.; Ramamurthy, R.; Samanta, D.; Shoer, L.; Amour, A. St; Tan, L. H.; Yemenicioglu, S.; Wang, X.; Ghani, T.
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
PowerVia increases the efficiency of power delivery by adding back-side interconnects [1]. It also improves performance by relaxing the minimum front-side interconnect pitch and by optimizing them for signaling. Research to further improve performance and density synergistically with PowerVia includes back-side device contacts and device stacking. In this paper, we present an experimental demonstration of a novel cell architecture with back-side device contacts and back side power delivery. Keywords: back-side power delivery, back-side contacts, BSCON.