학술논문

MSC-PoL: Hybrid GaN–Si Multistacked Switched-Capacitor 48-V PwrSiP VRM for Chiplets
Document Type
Periodical
Source
IEEE Transactions on Power Electronics IEEE Trans. Power Electron. Power Electronics, IEEE Transactions on. 38(10):12815-12833 Oct, 2023
Subject
Power, Energy and Industry Applications
Aerospace
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
General Topics for Engineers
Nuclear Engineering
Signal Processing and Analysis
Transportation
Switches
Voltage control
Inductors
Computer architecture
Capacitors
Magnetics
Rails
Chiplet
coupled inductor
CPU voltage regulation module (VRM)
point of load (PoL)
power supply in package (PwrSiP)
switched capacitor (SC)
Language
ISSN
0885-8993
1941-0107
Abstract
This article presents a multistack switched-capacitor point-of-load (MSC-PoL) voltage regulation module (VRM) with coupled magnetics for ultrahigh-current chiplet systems. In the MSC-PoL architecture, the stacked switched-capacitor cells split the high input voltage into several intermediate voltage rails, which are loaded with the switched-inductor cells to achieve soft charging and voltage regulation. Automatic capacitor voltage balancing and inductor current sharing are realized during the soft charging process. Many inductors of the switched-inductor cells are coupled into one and operated in interleaving to reduce the inductor current ripple and boost the transient speed. A 48-to-1-V/450-A VRM containing two MSC-PoL modules is built and tested, leveraging high-voltage GaN devices for the front end and high-current silicon devices for the back end. Two ladder-structured coupled inductor designs are developed and compared, one of which installs a leakage magnetic plate to adjust the leakage inductance for lower current ripple. Featuring 3-D stacked packaging, the entire power stage, gate drivers, and bootstrap circuits of one MSC-PoL module are enclosed into a $\frac{1}{16}$-brick/0.31-in$^{3}$/6-mm-thick package. The peak efficiency, the full-load efficiency, and the full-load power density (including both gate loss and size) of the MSC-PoL prototype with and without using the leakage plate are 91.7% and 89.5%, 85.8% and 85.6%, and 621 and 724 W/in$^{3}$, respectively. The 6-mm-thick MSC-PoL converter can be embedded into the chiplet or CPU socket, enabling power supply in package for extreme efficiency, density, and control bandwidth.