학술논문

Design of a Low-Power and Area-Efficient LDO Regulator Using a Negative-R-Assisted Technique
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 70(10):3892-3896 Oct, 2023
Subject
Components, Circuits, Devices and Systems
Regulation
Gain
Resistance
Regulators
Mathematical models
Transconductance
Transistors
Low-power
area-efficient
low dropout (LDO) regulator
negative-R-assisted LDO
power management IC (PMIC)
Language
ISSN
1549-7747
1558-3791
Abstract
To mitigate the non-ideal virtual ground at the feedback node of a low dropout (LDO) regulator, this brief presents an LDO with an off-chip capacitor that uses a negative-R assisted technique, which enhances its performance, including load/line regulation and power supply rejection (PSR). This technique enables the LDO to achieve improved performance despite the small size of the pass transistor, resulting in low-power and area-efficient LDO regulators. The proposed negative-R-assisted LDO provides 100 mA, with load regulation of 0.09 mV/mA, line regulation of 6 mV/V, and PSR of -31 dB. The proposed negative-R-assisted LDO was implemented with 150 nm transistors in a 28 nm standard CMOS process with an active area of 4, $200~\mu \text{m}\mathrm {^{2}}$ . The proposed LDO achieves a superior figure-of-merit (FoM) of 13.5 ps (FoM1) and 0.057 ps $\cdot \mathrm {mm^{2}}$ (FoM2).