부산대학교 도서관

We presented a novel hardware architecture that uses dual Benes networks to accelerate Convolutional Neural Network (CNN) algorithms. This architecture can reduce the need for high-speed buses and maintain a high-speed connection between execution units and memories. Also, this design can work with multiple neural network models by changing the Benes network configuration only due to the reorderability of the non-blocking networks. The proposed architecture can save the time of re-implementing the hardware design. Thus, this architecture can act as a general CNN accelerator. We successfully implemented our CNN accelerator on the Xilinx Virtex UltraScale+ VU19P and evaluated it by running the CNN model LeNet-5.