학술논문

CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme
Document Type
Conference
Source
2023 IEEE 41st VLSI Test Symposium (VTS) VLSI Test Symposium (VTS), 2023 IEEE 41st. :1-8 Apr, 2023
Subject
Components, Circuits, Devices and Systems
Resistance
Productivity
Protocols
Supply chains
Automata
Authentication
Watermarking
IP Watermarking
IP Authentication
Cellular Automata
Language
ISSN
2375-1053
Abstract
The ever-increasing propensity for intellectual property (IP) reuse has reduced the design productivity gap in the supply chain. As a consequence, protecting IPs has become more difficult since IP vendors now make their IPs more flexible so that they can be reused in other designs for greater profits. This has made IP piracy and infringement easier than ever. IP watermarking can detect IP piracy and infringement and it has been an active research topic for the past decade. Various watermarking techniques have been discussed in the literature that embed circuitry into IP to provide proof of ownership. But, in most RT-level watermarking methods, the watermarking circuit is separate from IP functionality and can be easily identified and tampered with. In this paper, we propose CAPEC, a Cellular Automata (CA) guided watermarking technique that embeds watermarking circuits into the don’t care states of the FSM. The watermarking function is a set of configurable CA rules tightly coupled with the functional states of the FSM. CAPEC generates a signature in a challenge-response-based protocol, is resistant to identification, tampering, and removal attacks, and has minimal overhead. We also analyze and evaluate the efficiency of the technique and its resilience to different attacks for varying challenge size and CA rules. After watermarking different benchmarks, the watermark overhead was found to be negligible and formal verification proved no changes to the functional circuit.