부산대학교 도서관

III-V co-integration is less mature compared to Si/Ge CMOS due to their inferior pMOS device performance. This letter adopts a novel quaternary InGaAsSb channel material in a core-shell vertical nanowire structure to overcome the limitations. A gate-last process achieves self-alignment of the drain and gate contacts. The improved electrostatics with short gate length ${L}_{\text {g}}$ = 60 nm results in a good balance between the on-state and the off-state performances. The presented devices demonstrate the lowest inverse subthreshold slope ( ${S}$ ) for a III-V PMOS with ${S}_{\text {sat}}$ = 75 mV/dec with significant ${I}_{\text {on}}/{I}_{\text {off}}$ ratio of $10^{{4}}$ and ${I}_{\text {min}} < $ 1 nA/ $\mu \text{m}$ . The substantial improvement in the device performance compared to earlier reports provides an opportunity for III-V complementary field-effect transistor integration.