학술논문

Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 70(8):3234-3243 Aug, 2023
Subject
Components, Circuits, Devices and Systems
Clocks
Random access memory
Digital signatures
Protocols
Hardware acceleration
Systems architecture
NIST
Post-quantum
cryptography
PQC
crystals-dilithium
FPGA
hardware
ASIC
hardware accelerator
Language
ISSN
1549-8328
1558-0806
Abstract
The looming threat of an adversary with quantum computing capability led to a worldwide research effort towards identifying and standardizing novel post-quantum cryptographic primitives. Post-standardization, all existing security protocols will need to support efficient implementation of these primitives. In this work, we contribute to these efforts by reporting the smallest implementation of CRYSTALS-Dilithium, one of the chosen post-quantum digital signature scheme for NIST standardization process. By invoking multiple optimizations to leverage parallelism, pre-computation and memory access sharing, we obtain an implementation that could be fit into one of the smallest Zynq FPGA. On Zynq Ultrascale+, our design achieves an improvement of about 36.7%/35.4%/42.3% in Area $\times $ Time (LUTs $\times \text{s}$ ) trade-off for KeyGen/Sign/Verify respectively over state-of-the-art implementation. We also evaluate our design as a co-processor on three different hardware platforms and compare the results with software implementation, thus presenting a detailed evaluation of CRYSTALS-Dilithium targeted for embedded applications. Further, on ASIC using TSMC 65nm technology, our design requires 0.227mm 2 area and can operate at a frequency of 1.176 GHz. As a result, it only requires $53.7\mu \text{s}/96.9\mu \text{s}/57.7\mu \text{s}$ for KeyGen/Sign/Verify operation for the best-case scenario.