학술논문
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking
Document Type
Conference
Author
Source
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) Design automation conference Design Automation Conference, 2002. Proceedings. 39th. :819-823 2002
Subject
Language
ISSN
0738-100X
Abstract
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bristol was introducing pseudo-random testing (using Specman) and property checking (using GateProp) into their verification flows and thus provides a good opportunity to compare these two techniques with the existing strategy of directed testing using VHDL bus functional models.