부산대학교 도서관

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm 2 area and has an input referred noise of 2.7 $\mu \text {V}_{\text {rms}}$ . It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2 ${\text {e}^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180Kelvin.