학술논문
Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits
Document Type
Conference
Author
Source
2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID) VLSID VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), 2023 36th International Conference on. :98-103 Jan, 2023
Subject
Language
ISSN
2380-6923
Abstract
Recent CMOS scaling incessantly focuses on improving density, speed, area, and power consumption in digital circuits which is increasingly less applicable to analog/mixed-signal circuits. This paper proposes various practical techniques to overcome technology challenges in several common analog/mixed-signal circuits in 5nm CMOS. Issues addressed include high leakage in dummy devices due to continuous active area layout style, large parasitics in ring oscillators, and gate-induced drain leakage in SAR ADC sampling switches.