학술논문

A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit
Document Type
Periodical
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 31(6):749-761 Jun, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Object detection
Computational modeling
Hardware
Quantization (signal)
Neural networks
Field programmable gate arrays
Deep learning
Binarized neural network (BNN)
convolutional neural network (CNN)
field-programmable gate array (FPGA)
low-power design
object detection
Language
ISSN
1063-8210
1557-9999
Abstract
Object detection algorithms using convolutional neural networks (CNNs) achieve high detection accuracy, but it is challenging to realize real-time object detection due to their high computational complexity, especially on resource-constrained mobile platforms. In this article, we propose an algorithm-hardware co-optimization approach to designing a real-time object detection system. We first develop a compact object detection model based on a binarized neural network (BNN), which employs a new layer structure, the DenseToRes layer, to mitigate information loss due to deep quantization. We also propose an efficient object detection processor that runs object detection with high throughput using limited hardware rescources. We develop a resource-efficient processing unit supporting variable precision with minimal hardware overheads. Implemented in field-programmable gate array (FPGA), the object detection processor achieves 64.51 frames/s throughput with 64.92 mean average precision (mAP) accuracy. Compared to prior FPGA-based designs for object detection, our design achieves high throughput with competitive accuracy and lower hardware implementation costs.