학술논문
A 12.8-Gb/s 0.5-pJ/b Encoding-Less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
Document Type
Periodical
Author
Source
IEEE Solid-State Circuits Letters IEEE Solid-State Circuits Lett. Solid-State Circuits Letters, IEEE. 6:65-68 2023
Subject
Language
ISSN
2573-9603
Abstract
A 12.8-Gb/s 0.5-pJ/b inductive coupling interchip wireless communication interface for a 3D-stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET process. A new clocked hysteresis comparator that eliminates encoding for synchronous communication achieves 1.49 times higher data rate and 36% lower energy consumption compared to conventional synchronous communication using Manchester encoding. Interchip communication at 0.5-pJ/b 12.8 Gb/s was confirmed using test chips. The proposed interface for a 4-hi 3D-stacked SRAM module achieves a 1.7-TB/s/mm 2 IO area efficiency and 111-GB/s/W bandwidth per power, representing a two-orders-of-magnitude improvement in area efficiency over a state-of-the-art interface for a 3D-stacked SRAM with competitive per-power bandwidth.