부산대학교 도서관

The semiconductor industry is turning to advanced heterogeneous integration to achieve significant system-level performance improvements. The industry is looking to replace current packaging technologies such as flip-chip ball grid array (FC-BGA) and wafer-level chip scale packaging (WLCSP) with fanout wafer level packaging (FOWLP) due to its ability to allow for higher density interconnects in a smaller form factor with lower cost and better electrical performance. The combination of smaller devices and the desire for thousands of chip-to-chip connections are driving an unprecedented need for shrinking the device bond pad pitch. Currently running at volumes in the millions per day on 300mm round format, Deca's M-Series™ fan-out technology and Adaptive Patterning® (AP) are being scaled up to 600mm for production at ASE. The extension of the first and introduction of our second-generation M -Series & AP technologies will be explored as they deliver ultra-high-density 20µm area array bond pad pitch through a unique design-during-manufacturing process using Laser Direct Imaging (LDI) with 250nm digital patterns.