학술논문
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features
Document Type
Periodical
Author
Ryu, Y.; Ahn, S.; Lee, J.H.; Park, J.; Kim, Y.K.; Kim, H.; Song, Y.G.; Cho, H.; Cho, S.; Song, S.H.; Lee, H.; Shin, U.; Ahn, J.; Ryu, J.; Lee, S.; Lim, K.; Lee, J.; Park, J.H.; Jeong, J.; Joo, S.; Cho, D.; Kim, S.Y.; Lee, M.; Kim, M.; Kim, J.; Kang, H.G.; Kim, S.; Kwon, Y.; Byun, Y.Y.; Lee, K.; Park, S.; Youn, J.; Sohn, K.; Hwang, S.
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 58(4):1051-1061 Apr, 2023
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
This article proposes practical design techniques to enhance performance and reliability of 1024 GB/s high-bandwidth memory-3 (HBM3). Effective data-bus design methods are applied to transfer data from multi-bank to a data-bus with a sufficient data fetch margin. A symbol-based on-die error-correcting code (OD-ECC) to correct a 16-bit error, bounded by a sub-wordline (WL), and parallelized data-bus inversion (DBI) are implemented. Error check and scrub (ECS) mode and repair capability check (RCC) mode with an internal serial interface are designed to support system reliability, availability, and serviceability (RAS). A memory built-in self-test (MBIST) provides a unified at-speed test with programmability based on test-set units (TUs). A 16 GB HBM3 fabricated in the third generation of the 10 nm class DRAM process achieves a bandwidth up to 1024 GB/s (8 Gb/s/pin) and provides stable operation at a high temperature (e.g., 105 °C) while improving an error detection rate by 92.2%.