부산대학교 도서관

Front-end electronics (FEEs) equipped with high-speed digitizers are being used and proposed for future nuclear detectors. Recent literature reveals that deep learning models, especially 1-D convolutional neural networks (NNs), are promising when dealing with digital signals from nuclear detectors. Simulations and experiments demonstrate the satisfactory accuracy and additional benefits of NNs in this area. However, specific hardware accelerating such models for online operations still needs to be studied. In this work, we introduce PulseDL-II , a system-on-chip (SoC) specially designed for applications of event feature (time, energy, and so on) extraction from pulses with deep learning. Based on the previous version, PulseDL-II incorporates an reduced instruction set computer (RISC) CPU into the system structure for better functional flexibility and integrity. The NN accelerator in the SoC adopts a three-level (arithmetic unit (AU), processing element (PE), and NN) hierarchical architecture and facilitates parameter optimization of the digital design. Furthermore, we devise a quantization scheme compatible with deep learning frameworks (e.g., TensorFlow) within a selected subset of layer types. We validate the correct operations of PulseDL-II on field programmable gate arrays (FPGAs) alone and with an experimental setup comprising a direct digital synthesis (DDS) and analog-to-digital converters (ADCs). The proposed system achieved 60-ps time resolution and 0.40% energy resolution at a signal-to-noise ratio (SNR) of 47.4 dB.