학술논문

Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 42(9):3067-3077 Sep, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Layout
Optimization
Lithography
Multiprotocol label switching
Law
Resists
Reinforcement learning
Design for manufacturability
double patterning
inverse lithography technique (ILT)
reinforcement learning (RL)
Language
ISSN
0278-0070
1937-4151
Abstract
Multiple patterning lithography decomposition (MPLD) and mask optimization enable the ever-shrinking device feature sizes far below the lithography system limit. Conventional MPLD is solved by mathematical programming or graph-based approaches, where a set of predetermined rules is indispensable to identify the conflicts to be resolved. In this article, we explore rule-free layout decomposition following a simple but sweet principle, let the mask optimizer “teach” the layout decomposer how to generate suitable decompositions. Our flow includes a reinforcement-learning-based layout decomposer and a deep-learning-based mask optimizer. Without any handcrafted rules, our framework can perform competitively and even surpass the state-of-the-art rule-based methods with notable $(7\times \sim 63\times)$ turn-around-time speedup.