부산대학교 도서관

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 um x 248 um. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are +/-0.6 LSB and +/-0.75 LSB, respectively. The jitter from -25 C to 20 C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.
Comment: 7 pages, 8 figures