학술논문
Qualification method for a 1 MGy-tolerant front-end chip designed in 65 nm CMOS for the read-out of remotely operated sensors and actuators during maintenance in ITER
Document Type
Article
Author
Source
In Fusion Engineering and Design October 2015 96-97:1002-1005
Subject
Language
ISSN
0920-3796
Abstract
This paper describes the radiation qualification procedure for a 1MGy-tolerant Application Specific Integrated Circuit (ASIC) developed in 65nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (<10kHz) sensors. In addition the IC is able to multiplex the digitized sensor signals. To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed. The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.