학술논문
A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience.
Document Type
Article
Author
Source
Subject
*FLIP-flop circuits
*TRANSISTORS
*TECHNOLOGY
*RADIATION hardening (Electronics)
*SOFT errors
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Language
ISSN
0018-9499
Abstract
A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits. [ABSTRACT FROM AUTHOR]