부산대학교 도서관

Current starved delay elements (CSDEs) are among the popular architectures to manipulate rising or falling edges of signals in order to meet timing requirements. The digitally controllable generations of these topologies are now monotonic and reasonably power efficient, but they lack linearity in full range. Inherently, this subject may not seem problematic because by setting the dimensions of the design elements the desired delay can be acquired. However, in case that a chain of incremental delays are required, we tend to employ more linear designs. In this paper two improvements in linearity are examined for two known CS designs. Both of the topologies are in 0.18μm technology and meet appropriate design parameters like power, area and monotonic response. [ABSTRACT FROM AUTHOR]