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COMPUTER 72, ISLANDS OF APPLICATION, TECHNICAL CONFERENCE, PAPERS, 1972.
Academic Journal
Nichols, Jon A.
;
Allan III, John J.
;
Yoshida, Kenji
;
Nakayama, Nobutoshi
;
Satoh, Toshiko
;
Tamaru, Keikichi
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MOSFET statistical modeling method using an intermediate model.
Academic Journal
Kondo, Masaki
;
Onodera, Hidetoshi
;
Tamaru, Keikichi
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Jan2001, Vol. 84 Issue 1, p57-66. 10p.
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A method for improving reusability of design procedures of analog circuits—storage and reuse of design constraints and uncertain parameters.
Academic Journal
Morie, Takashi
;
Onodera, Hidetoshi
;
Tamaru, Keikichi
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. May2000, Vol. 83 Issue 5, p62-75. 14p.
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A Cyclic Switched Capacitor A-D, D-A Converter.
Academic Journal
Onodera, Hidetoshi
;
Tateishi, Tetsuo
;
Tamaru, Keikichi
Electronics & Communications in Japan, Part 2: Electronics
. Sep87, Vol. 70 Issue 9, p56-65. 10p.
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A Method of Extracting MOSFET Parameters with Small Model Dependency Using a Common Intermediate Model.
Academic Journal
Kondo, Masaki
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Onodera, Hidetoshi
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Tamaru, Keikichi
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Sep96, Vol. 79 Issue 9, p76-87. 12p.
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A Method for Analog Circuit Design That Stores and Reuses Design Procedures.
Academic Journal
Morie, Takashi
;
Onodera, Hidetoshi
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Tamaru, Keikichi
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Mar1994, Vol. 77 Issue 3, p87-96. 10p.
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Behavioral Verification of CPUs Using Functional Information Extraction.
Academic Journal
Ohmura, Masahiko
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Tamaru, Keikichi
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Yasuura, Hiroto
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Mar1994, Vol. 77 Issue 3, p52-61. 10p.
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Branch-and-Bound Placement for Building Block Layout.
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Onodera, Hidetoshi
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Taniguchi, Yo
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Tamaru, Keikichi
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Jul93, Vol. 76 Issue 7, p15-26. 12p.
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Functional Information Extraction from Combinational Circuits.
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Ohmura, Nasahiko
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Yasuura, Hiroto
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Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Nov91, Vol. 74 Issue 11, p28-38. 11p.
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A Functional Memory Type Parallel Processor Architecture for Solving Combinational Problems.
Academic Journal
Yasuura, Hiroto
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Tsujimoto, Taizou
;
Tamaru, Keikichi
Electronics & Communications in Japan, Part 3: Fundamental Electronic Science
. Jan90, Vol. 73 Issue 1, p23-31. 9p.
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