부산대학교 도서관

The one hundred and thirty-one papers in this collection include the following:\ Nikrouz\ Faroughi and Michael A.\ Shanblatt, An improved systematic method for constructing systolic arrays from algorithms (pp.\ 26--34); Kye S.\ Hedlund, Aesop: a tool for automated transistor sizing (pp.\ 114--120); S.\ Chowdhury [Salim U.\ Chowdhury], An automated design of minimum-area IC power/ground nets (pp.\ 223--229); R.\ Rajsuman, Y. K.\ Malaiya and A. P.\ Jayasumana, On accuracy of switch-level modeling of bridging faults in complex gates (pp.\ 244--250); Steven J.\ Friedman and Kenneth J.\ Supowit, Finding the optimal variable ordering for binary decision diagrams (pp.\ 348--356); Philip S.\ Yu, C. M.\ Krishna and Yann-Hang\ Lee, VLSI circuit testing using an adaptive optimization model (pp.\ 399--406); Andrzej\ Kraśniewski and Sławomir\ Pilarski, Circular self-test path: a low-cost BIST technique (pp.\ 407--415); D. F.\ Wong and C. L.\ Liu [Chung Laung\ Liu], Array optimization for VLSI synthesis (pp.\ 537--543); Robert L.\ Maziasz and John P.\ Hayes, Layout optimization of CMOS functional cells (pp.\ 544--551); Chidchanok\ Lursinsap and Daniel\ Gajski, Improving a PLA area by pull-up transistor folding (pp.\ 608--614); Loc Bao\ Nguyen, Marek A.\ Perkowski and Nahum B.\ Goldstein, PALMINI---fast Boolean minimizer for personal computers (pp.\ 615--621); P.\ Mazumder, J. H.\ Patel and W. K.\ Fuchs, Design and algorithms for parallel testing of random access and content addressable memories (pp.\ 688--694); Ching-Farn E.\ Wu, Anthony S.\ Wojcik and Lionel M.\ Ni, A rule-based circuit representation for automated CMOS design and verification (pp.\ 786--792); Siegmar\ Koeppe, Optimal layout to avoid CMOS stuck-open faults (pp.\ 829--835). \par \edref {Some of the papers are being reviewed individually.}