부산대학교 도서관

This work reports the performance evaluation of an SDR readout system based on the latest generation (Gen3) of AMD’s Radio-Frequency System-on-Chip (RFSoC) processing platform, which integrates a full-stack processing system and a powerful FPGA with up to 32 high-speed and high-resolution 14-bit Digital-to-Analog Converters and 14-bit Analog-to-Digital Converters. The proposed readout system uses a previously developed multi-band, double-conversion IQ RF-mixing board targeting a multiplexing factor of approximately 1000 bolometers in a bandwidth between 4 and 8 GHz, in line with state-of-the-art microwave SQUID multiplexers. The characterization of the system was performed in two stages, under the conditions typically imposed by the multiplexer and the cold readout circuit: first, in transmission, showing that noise and spurious levels of the generated tones are close to the values imposed by the cold readout, and second, in RF loopback, presenting noise values better than −100 dBc/Hz totally in agreement with the state-of-the-art readout systems. It was demonstrated that the RFSoC Gen3 device is a suitable enabling technology for the next generation of superconducting detector readout systems, reducing system complexity, increasing system integration, and achieving these goals without performance degradation.