학술논문
Selective area halogen doping to achieve dual gate oxide thickness on a wafer
Document Type
Patent
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Abstract
A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is desired. These areas are then implanted with a halogen species such as fluorine or chlorine, to retard oxidation. The pattern (36) is then removed and an oxidation step is performed. Oxidation is selectively retarded in areas (14) previously doped with the halogen species but not in the remaining areas (12). Thus, a single oxidation step may be used to form gate oxides (20,22) of different thicknesses.