학술논문
Semiconductor memory circuit equipped with a column addressing circuit having a shift register
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Patent
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Abstract
The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit normally comprising a counter constitutes a shift register in a column addressing circuit at a preceding stage of a column address buffer so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.