학술논문

Method and Processor for Performing a Floating-Point Instruction Within a Processor
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Patent
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Abstract
The invention relates to a method for performing floating-point instructions within a processor of a data processing system is described, wherein an input of said floating-point instruction comprises a normal or a denormal floating-point number. Said method comprises the steps of storing said floating-point number, normalization of said floating-point number by counting the leading zeros of the mantissa, shifting the fraction part to the left by the number of leading zeros and simultaneously decrementing the exponent by one for every position that the fraction part is shifted to the left, wherein it the input is a normal floating point number the normalization is done after counting no leading zero of the mantissa, execution of a floating point instruction, wherein said normalized floating-point number is utilized as input for the floating point instruction, and storing of a floating-point result. Furthermore a processor to be used to perform said method is described.