학술논문

SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD
Document Type
Patent
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Abstract
A semiconductor integrated circuit has a scan chain with a scan clock signal line for clocking scan flip-flops and a scan test signal line for transferring scanning data into and out of the scan flip-flops. Part of the scan test signal line is routed adjacently parallel to the scan clock signal line to shield the scan clock signal line from electrical noise during normal operation, when the scan test signal line is held at a fixed potential. Separate shield lines are used to shield parts of the scan clock signal line not shielded by the scan test signal line. Use of a combination of shield lines and the scan test signal line to shield the scan clock signal line saves space and conserves routing resources.