부산대학교 도서관

Method of fabricating an integrated memory device including the steps of providing a semiconductor substrate, including an array region and a support region; providing GC-lines in said array region and in said support region, wherein the GC-lines in said support region have a first height; providing in the array region bit line contacts projecting above said GC-lines, wherein said bit line contacts have a second height being higher than said first height; providing a first isolation layer, the maximum height of said GC-lines in said support region including the coverage of said first isolation layer being lower than said second height; providing a second isolation layer on said first isolation layer; and polishing said first isolation layer and said second isolation layer, such that a planar surface of the integrated memory device is provided and such that said bit line contacts are exposed.