학술논문
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
Document Type
Journal Article
Author
Source
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2012, E95.A(8):1359
Subject
Language
English
ISSN
0916-8508
1745-1337
1745-1337
Abstract
This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.