부산대학교 도서관

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0[sup.∘] output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm[sup.2] core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.
Author(s): Jing Kang [1,2]; Fei Liu (corresponding author) [1,*]; Ya Hai [1,2]; Yongshan Wang [1,2] 1. Introduction With the advantages of high stability [1,2,3] and strong portability [4,5,6,7], the all [...]