학술논문
A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates
Document Type
Article
Author
Source
In: Solid-State Electronics . (Solid-State Electronics, April 2006, 50(4):620-625)
Subject
Language
English
ISSN
00381101