학술논문
Improving the hardware utilization efficiency of partially parallel LDPC decoder with scheduling and sub-matrix decomposition
Document Type
Conference Paper
Author
Source
In: Proceedings - IEEE International Symposium on Circuits and Systems , 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. (Proceedings - IEEE International Symposium on Circuits and Systems, 2009, :2233-2236)
Subject
Language
English
ISSN
02714310