학술논문
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
Document Type
Conference Paper
Author
Greene, B.; Liang, Q.; Wang, Y.; Cai, M.; Liang, Y.; Saroop, S.; Rotondaro, A.; Han, S.-J.; Mo, R.; McStay, K.; Ku, S.; Kumar, M.; Dirahoui, B.; Tamweber, F.; Lee, W.-H.; Steigerwalt, M.; Holt, J.; Belyansky, M.; Yin, H.; Chan, K.; Angyal, M.; Ogunsola, O.; Zhuang, L.; Yan, H.; Sleight, J.; Guo, D.; Mittl, S.; Ioannou, D.; Wu, E.; Chudzik, M.; Park, D.-G.; Mocuta, D.; Maciejewski, E.; Henson, K.; Leobandung, E.; Amarnath, K.; Cheng, J.; Pal, R.; Yang, B.; Weijtmans, H.; Black, L.; Ramani, K.; Lee, D.; Van Meer, H.; Child, C.; Permana, D.; Brown, D.; Luning, S.; Schaeffer, J.; Samavedam, S.; Turner, M.; Chowdhury, M.; Aimé, D.; Min, B.; Zaleski, M.
Source
In: Digest of Technical Papers - Symposium on VLSI Technology , 2009 Symposium on VLSI Technology, VLSIT 2009. (Digest of Technical Papers - Symposium on VLSI Technology, 2009, :140-141)
Subject
Language
English
ISSN
07431562