학술논문
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
Document Type
Conference Paper
Author
Mertens, H.; Hosseini, M.; Chiarella, T.; Zhou, D.; Wang, S.; Mannaert, G.; Dupuy, E.; Radisic, D.; Tao, Z.; Oniki, Y.; Hikavyy, A.; Rosseel, R.; Mingardi, A.; Choudhury, S.; Gowda, P.P.; Sebaai, F.; Peter, A.; Vandersmissen, K.; Soulie, J.P.; Keersgieter, A.D.; Lima, L.P.B.; Cavalcante, C.; Batuk, D.; Martinez, G.T.; Geypen, J.; Seidel, F.; Paulussen, K.; Favia, P.; Boemmels, J.; Loo, R.; Wong, P.; Marquez, A.S.; Chan, B.T.; Mitard, J.; Subramanian, S.; Demuynck, S.; Litta, E.D.; Horiguchi, N.; Samavedam, S.; Biesemans, S.
Source
In: Digest of Technical Papers - Symposium on VLSI Technology , 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. (Digest of Technical Papers - Symposium on VLSI Technology, 2023, 2023-June)
Subject
Language
English
ISSN
07431562