학술논문
Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance
Document Type
Conference
Author
Mercha, A.; Redolfi, A.; Stucchi, M.; Minas, N.; Van Olmen, J.; Thangaraju, S.; Velenis, D.; Domae, S.; Yang, Y.; Katti, G.; Labie, R.; Okoro, C.; Zhao, M.; Asimakopoulos, P.; De Wolf, I.; Chiarella, T.; Schram, T.; Rohr, E.; Van Ammel, A.; Jourdain, A.; Ruythooren, W.; Armini, S.; Radisic, A.; Philipsen, H.; Heylen, N.; Kostermans, M.; Jaenen, P.; Sleeckx, E.; Sabuncuoglu Tezcan, D.; Debusschere, I.; Soussan, P.; Perry, D.; Van der Plas, G.; Cho, J.H.; Marchal, P.; Travaly, Y.; Beyne, E.; Biesemans, S.; Swinnen, B.
Source
2010 Symposium on VLSI Technology VLSI Technology (VLSIT), 2010 Symposium on. :109-110 Jun, 2010
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.