학술논문
Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions
Document Type
Conference
Author
Source
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Solid-State Device Research Conference Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European. :445-448 2005
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we endeavor to integrate a low temperature selective epitaxial growth process and a low temperature NiSi process to form low resistance S/D contacts. Our experimental results show 34% and 11% improvement in parasitic S/D resistance of N-and P-channel multiple gate FETs with less than 20 nm wide fins respectively.