학술논문
A low-power 12-b analog-to-digital converter with on-chip precision trimming
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 28(4):455-461 Apr, 1993
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1- mu m CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW.ETX