학술논문
Word-line architecture for highly reliable 64-Mb DRAM
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 27(4):603-609 Apr, 1992
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10/sup 5/ times reliability improvement and a 0.3 approximately 1.8-V larger word-line voltage margin to write ONE data into the cell.ETX