학술논문
PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology
Document Type
Conference
Author
Song, L.; Liang, Y.; Onoda, H.; Lai, C. W.; Wallner, T. A.; Pofelski, A.; Gruensfelder, C.; Josse, E.; Okawa, T.; Brown, J.; Williams, R.Q.; Holt, J.; Weijtmans, J.W.; Greene, B.; Utomo, H. K.; Lee, S. C.; Nair, D.; Zhang, Q.; Zhu, C.; Wu, X.; Sherony, M.; Lee, Y. M.; Henson, W. K.; Divakaruni, R.; Kaste, E.
Source
Proceedings of Technical Program of 2012 VLSI Technology, System and Application VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on. :1-2 Apr, 2012
Subject
Language
ISSN
1524-766X
1930-8868
1930-8868
Abstract
The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.