학술논문
Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems
Document Type
Periodical
Author
Source
IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 55(2):672-686 Mar, 2008
Subject
Language
ISSN
1549-8328
1558-0806
1558-0806
Abstract
We propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25μm- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.