학술논문

A comprehensive and accurate latency model for Network-on-Chip performance analysis
Document Type
Conference
Source
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific. :323-328 Jan, 2014
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Analytical models
Routing
Delays
Algorithm design and analysis
Queueing analysis
Performance analysis
Mathematical model
Language
ISSN
2153-6961
2153-697X
Abstract
In this work, we propose a new, accurate, and comprehensive analytical model for Network-on-Chip (NoC) performance analysis. Given the application communication graph, the NoC architecture, and the routing algorithm, the proposed framework analyzes the links dependency and then determines the ordering of queuing analysis for performance modeling. The channel waiting times in the links are estimated using a generalized G/G/1/K queuing model, which can tackle bursty traffic and dependent arrival times with general service time distributions. The proposed model is general and can be used to analyze various traffic scenarios for NoC platforms with arbitrary buffer and packet lengths. Experimental results on both synthetic and real applications demonstrate the accuracy and scalability of the newly proposed model.