학술논문
Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA
Document Type
Conference
Source
2015 International Conference on Field Programmable Technology (FPT) Field Programmable Technology (FPT), 2015 International Conference on. :24-31 Dec, 2015
Subject
Language
Abstract
Modern computer networks need components that can evolve to support both the latest bandwidth demands and new protocols and features. To address this need, we propose a new programmable packet processor architecture built from an FPGA containing an embedded Network-on-Chip (NoC). The architecture is highly flexible, providing more programmability than is possible in an ASIC-based design, while supporting throughputs of 400 and 800 Gb/s. Additionally, we show that our design is 1.7× and 3.2× more area efficient, and achieves 1.5× and 3.7× lower latency than the best previously proposed FPGA-based packet processor on complex and simple applications, respectively. Lastly, we explore various ways a designer can take advantage of the flexibility available in this architecture.