학술논문

A Chip-Level Verification Method for Programmable Vision Chip Based on Deep Learning Algorithms
Document Type
Conference
Source
2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM) Integrated Circuits and Microsystems (ICICM), 2020 IEEE 5th International Conference on. :281-284 Oct, 2020
Subject
Components, Circuits, Devices and Systems
Integrated circuit modeling
Computer architecture
Computer vision
Deep learning
Convolution
Computational modeling
Quantization (signal)
deep learning
chip-level verificaition
vision chip
Language
Abstract
The past five years has witnessed tremendous success of deep learning (DL) algorithm in the computer vision field, attributing to its high degree of accuracy on numerous visual tasks. Unfortunately, for the development of programmable vision chips, algorithm verification remains a major challenge due to the high computational complexity of the DL neural network. In this paper, we propose a novel chip-level verification method to address the common issues including low efficiency and poor reusability in verifying vision chips. In contrast to the block-level verification technique, this method focuses on the rapid implementation of the complete DL algorithm in chip-level verification, fulfilling the advanced demands of vision chip prior to the tape-out. The experiments on MobileNet-v1 indicates the significant reduction of the simulation time and debugging overheads via the proposed verification method.