학술논문
Compact model development for a new non-volatile memory cell architecture
Document Type
Conference
Source
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Microelectronic test structures Microelectronic Test Structures, 2002. ICMTS 2002. Proceedings of the 2002 International Conference on. :151-156 2002
Subject
Language
Abstract
An accurate SPICE compatible model for a novel flash memory device, the Top Floating Gate (TFG) cell, is described. This device can be integrated into CMOS processes with minimal disruption to the standard process. The cell is programmed and erased by Fowler Nordheim tunnelling, which is a low power operation thereby complying with a major requirement of system-on-chip applications. The development of an accurate model for flash memory is complicated by the variable nature of the cell. In standard flash memory, the threshold voltage and, therefore, the drain current of the cell vary as the cell is programmed or erased. In the TFG case, both the threshold voltage and series resistance vary which further complicates the model development. Our model has been found to be accurate over the full range of floating gate charge.