학술논문

A verification method for array-based vision chip using a fixed-point neural network simulation tool
Document Type
Conference
Source
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS) Circuits & Systems (LASCAS), 2020 IEEE 11th Latin American Symposium on. :1-4 Feb, 2020
Subject
Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Signal Processing and Analysis
Tools
Machine learning
Graphics processing units
Field programmable gate arrays
Unified modeling language
Hardware
Object oriented modeling
fixed-point simulation
algorithm level verification
vision chip
Language
ISSN
2473-4667
Abstract
In recent years, customized chips for accelerating deep learning algorithms have been continuously developed with some emerging challenges in the field of deep-learning-based vision chips. Considering the lack of algorithm-level verification tools, poor reusability of simulation code and low development efficiency in deep learning vision chip verification, a novel verification method, which is based on the fixed-point simulation tool, is proposed and utilized in the development of an array-based deep learning vision chip. This simulation tool, implemented by combination of Matlab and CUDA C, enables efficient and accurate verification of the vision chip by taking the classical MobileNet V1 as the benchmark. This method, integrated with the RTL and FPGA co-verification seamlessly, provides the golden reference and reliable verification during the entire development period of the vision chip.