학술논문

Measurement and simulation of interconnect capacitance variations
Document Type
Conference
Source
2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489 Statistical metrology Statistical Metrology, 2000 5th International Workshop on. :64-67 2000
Subject
General Topics for Engineers
Capacitance measurement
Circuit testing
Integrated circuit interconnections
Parasitic capacitance
Monitoring
Charge carrier processes
Semiconductor device measurement
Clocks
Manufacturing
Fluid flow measurement
Language
Abstract
In the work we present results of capacitance measurements monitoring variations of the interconnect process. The measurements are compared with a 3D-simulation. The comparison shows that for a standard parasitics extraction the capacitance can be underestimated by up to 30% compared to measured results. In order to overcome this discrepancy, in our extraction, we consider fill structures, line widening for yield enhancement and process specific effects such as optical proximity and highly trapezoidal cross section of the conductors. This leads to good agreement between measured and extracted results. We also evaluate in detail the contribution of each effect to the total capacitance.