학술논문

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory
Document Type
Periodical
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 36(12):1318-1320 Dec, 2015
Subject
Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
Logic gates
Flash memories
Threshold voltage
3D NAND flash memory
channel stacked NAND flash memory
stacked layer selection
LSM
SST threshold voltage setting
Language
ISSN
0741-3106
1558-0563
Abstract
In this letter, we propose a simplified channel-stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage ( $V_{\mathrm {th}}$ ) setting method that all the SSTs on each layer are set to targeted the $V_{\mathrm {th}}$ values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the $V_{\mathrm {th}}$ values of SSTs are set to the targeted $V_{\mathrm {th}}$ values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the $V_{\mathrm {th}}$ values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.