부산대학교 도서관

This paper presents a 2.85-mm2 0.4-6 GHz RF transceiver in 40-nm CMOS for low-cost and low-power IoT micro-hub applications. A single-path receiver (RX), an all-digital phase-locked loop (ADPLL), and a digital transmitter (DTX) (including a digital power amplifier, DPA) are integrated. In the RX, to reduce the chip area and power consumption, an inductor-less capacitive-feedforward wideband LNA and a Gm-C filter-based dc offset cancellation (Gm-C-DCOC) technique are proposed. The RX achieves a noise figure (NF) of 1.3-4.9 dB over 0.4-6 GHz while consuming 31 mW. The measured average IIP3, in-band P1dB, and calibrated IIP2 of the receiver are 4.5 dBm, −13.8 dBm, and 67.5 dBm, respectively. In the ADPLL, a calibration-free retiming fractional frequency dividing (FFD) scheme based on a parasitic insensitive digital phase interpolator is adopted, for releasing the narrow loop bandwidth limitation and achieving better phase noise without active noise cancellation techniques. In the DTX design, a piecewise bias voltage (PBV) technique is proposed for the AM-AM linearization. It achieves a peak output power of 22.5 dBm at 840 MHz with a drain efficiency of 60.2%. The DPA can work in a high-power mode without PBV and a middle-power mode with PBV for modulation with different complexity. Thanks to PBV, the DTX achieves 5.9%, 5.3% EVM for 2MS/s 16-QAM and 64-QAM without digital pre-distortion (DPD), respectively. The designed broadband reconfigurable transceiver can support most of the common IoT protocols in most key metrics.